Net6501 FPGA

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Contents

General Information

This page includes all the known information about the FPGA integration to the Net6501 up to now (05/2012).

The Net6501 is equipped with 2 FPGAs:

  • a Lattice MachXO CPLD used for CPU and power management (not user-programmable)
  • a Xilinx low-cost Spartan 3a FPGA which is user-programmable (this page is about this one)

The model number of the Xilinx chip is XC3S50A-VQG100(-C4).

Documentation can be found at the following URLs:

Status

A valid bitstream can be uploaded to the FPGA using the JTAG port (JP10), LEDs (Ready and Error) and GPIOs pins (JP8) can be controlled.

After bitstream upload, the OS running on the main processor becomes unresponsive (we observe the same behavior for the "Reset" button located next to the power connector. It might then be configurable ...).

Communication with main processor through LPC bus is still unsuccessful.

More information is needed about the minimal FPGA image requirements for normal system operations.

JTAG

Image:Net6501-jp10.jpg

P50 FPGA --> red "error" led (D10)
P52 FPGA --> green "ready" led (D8)
P43 CLK  --> Clock Frequency: 1,846,528 Hz (Measured using a BusPirate).

A custom-cut mini IDE 2.5" ide ribbon cable can be used to connect to the onboard JTAG port. Image:Net6501 FPGA jtag cable.jpg

UrJTAG can be used to configure the FPGA. Here is an example session:

jtag> cable JTAGkey
Connected to libftd2xx driver.
jtag> detect
IR length: 6
Chain length: 1
Device Id: 00000010001000010000000010010011 (0x02210093)
  Manufacturer: Xilinx (0x093)
  Part(0):      xc3s50a (0x2210)
  Stepping:     0
  Filename:     /usr/share/urjtag/xilinx/xc3s50a/xc3s50a (vq100 renamed !) 
jtag>
jtag> svf fpga.svf stop progress
detail: Parsing    960/967 ( 99%)detail:
detail: Scanned device output matched expected TDO values.
jtag>

LEDs can be toggled using JTAG commands:

jtag> instruction EXTEST
jtag> shift ir
jtag> set signal IO_P50 out 1 # turn red off
jtag> shift dr
jtag> set signal IO_P50 out 0 # turn red on
jtag> shift dr
jtag>

Build Environnement

Xilinx ISE WebPack can be found at the following URL:

http://www.xilinx.com/support/download/index.htm

It can be used program the FPGA with Verilog or VHDL.

The following basic constraint file (.ucf) can be used as a starting point:

NET "clk" LOC = "P43" ;

NET "red"  LOC   = "P50" ; 
NET "green"  LOC = "P52" ; 

NET "gpio0" LOC = "P98" ;
NET "gpio1" LOC = "P94" ;
NET "gpio2" LOC = "P93" ;
NET "gpio3" LOC = "P90" ;
NET "gpio4" LOC = "P89" ;
NET "gpio5" LOC = "P88" ;
NET "gpio6" LOC = "P86" ;
NET "gpio7" LOC = "P85" ;
NET "gpio8" LOC = "P84" ;
NET "gpio9" LOC = "P83" ;
NET "gpio10" LOC = "P78" ;
NET "gpio11" LOC = "P77" ;
NET "gpio12" LOC = "P73" ;
NET "gpio13" LOC = "P72" ;
NET "gpio14" LOC = "P71" ;
NET "gpio15" LOC = "P70" ;

This archive contains a quick and dirty Makefile based on the one from the Proxmark3 project.

With this you can generate a bitstream (.bit) and a programming file (.svf) from your Verilog code on the command line.

It was tested with Xilinx ISE Webpack 10.1.03.

Archive content:

  • Makefile: main Makefile
  • fpga.ucf: constraints file
  • fpga.v: verilog code (blinking LEDs sample code)
  • testbed.v: testbed code used for simulation and validation
  • xst.batch: script used to configure the synthesis tool
  • impact.batch: script used to generate programming file (.svf)
  • urjtag.batch: script used to upload the bitstream with UrJTAG and a JTAGKey compatible dongle (tested with a BusBlaster)

Makefile targets:

  • all: generate bitstream (.bit) then programming file (.svf)
  • clean: clean intermediate files and reports, but keep .bit and .svf files
  • cleanall: same as clean target but also remove .bit and .svf
  • sim: generate simulation script and data
  • wave: launch gtkwave with simulation data
  • upload: upload bitstream to the FPGA using UrJTAG


Note: the environment must be set before the Makefile can be used

$ source path_to_xilinx_webpack/ISE/settings32.sh

LPC Bus

No information yet.

Original Bitstream

A Xilinx bitstream of 54760 bytes designed for the xc3s50a FPGA can be found in the default BIOS image at offset 0x80.

$ file Net6501-FPGA-default-Xilinx.bit
Net6501-FPGA-default-Xilinx.bit: Xilinx BIT data - from net6501_fpga.ncd;UserID=0xFFFFFFFF - for s50avq100 - built 2011/12/02(0:11:32) - data length 0xd588

Replacing the bitstream in the BIOS image file might be a way to make it survive cold reboot. It is NOT recommended since it would probably brick your Net6501.

Demo

This video demonstrates glowing LEDs on the Soekris Net6501 using PWM.

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